1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit (IC) technology and, more particularly, to a semiconductor device having a high voltage MOS transistor allowing an increase in breakdown and fabricated with a more simple process.
2. Description of the Related Art
Dramatically growing semiconductor IC technology allows a variety of devices, such as transistors, capacitors and resistors, to be integrated in a single chip. Furthermore, various approaches to effectively embody such devices in the chip have been continuously studied and introduced in the art.
For example, modern silicon device technology attempts to combine logic technology represented by a CPU (central processing unit) for data processing and memory technology for data storing. Furthermore, such attempts intend to combine analog technology and RF technology together with logic and memory technologies.
In general, a transistor holds an important position common to logic and memory technologies. However, logic technology considers current drivability, whereas memory technology does reduced leakage current and improved breakdown voltage. Hence, it is required to effectively embody MOS (metal oxide semiconductor) transistors with different gate dielectrics in thickness on a single chip.
FIGS. 1 to 4 are cross-sectional views showing a method of fabricating a conventional semiconductor device having a high voltage MOS transistor. In the drawings, a reference character “A” indicates a region where a high voltage MOS transistor is formed. Hereinafter, this region will be referred to as a high voltage region. Similarly, a reference character “B” indicates a region where a low voltage MOS transistor is formed and which will be referred to as a low voltage region.
Referring to FIG. 1, a field area 3 is formed in a semiconductor substrate 1, defining an active area. In most cases, the substrate 1 is selectively etched to form a trench for the field area 3. Suitable insulating material is deposited to fill the trench and then planarized.
Next, gate oxide layers are formed on the substrate 1. That is, a relatively thick first gate oxide layer 5 is formed in the high voltage region (A), and a relatively thin second gate oxide layer 7 is formed in the low voltage region (B). Well-known various techniques may be used for forming the gate oxide layers 5 and 7 with different thickness. For example, a nitride layer is formed on the entire substrate 1 and removed from the high voltage region (A) by using typical photo etching process. Then the thick gate oxide layer 5 is thermally grown in the high voltage region. The remaining nitride layer is removed from the low voltage region (B), and the thin gate oxide layer 7 is thermally grown in the low voltage region.
Subsequently, a gate conductive layer 9, 11 is formed on the gate oxide layer 5, 7, and a first photoresist pattern 13 is formed thereon by using typical photo process. The first photoresist pattern 13 selectively exposes the high voltage region (A), fully covering the low voltage region (B).
Next, referring to FIG. 2, the gate conductive layer 9 in the high voltage region (A) is selectively etched until the first gate oxide layer 5 is exposed. Here, the first photoresist pattern 13 is used as an etch mask. As a result, a first gate electrode 9a is formed in the high voltage region (A).
Next, referring to FIG. 3, the first gate oxide layer 5 is selectively etched using the first photoresist pattern 13 as an etch mask. Here, the first gate oxide layer 5 may partially remain after etching. As a result, the first gate oxide layer 5 is composed of an unetched portion 5a under the first gate electrode 9a and a partially etched portion 5b remaining on the substrate 1. The remaining gate oxide layer 5b may act as a buffer layer during the subsequent ion implanting process. A low doping part 14 of a source/drain is formed in the substrate 1 through a shallow ion implantation.
Next, referring to FIG. 4, the first photoresist pattern 13 is removed, and a second photoresist pattern 15 is formed instead. The second photoresist pattern 15 selectively exposes the low voltage region (B), fully covering the high voltage region (A). Then, the gate conductive layer 11 is selectively etched using the second photoresist pattern 15 as an etch mask, so a second gate electrode 11a is formed in the low voltage region (B).
Thereafter, spacers are formed on sidewalls of the gate electrodes 9a and 11a, and a high doping part of the source/drain is formed in the substrate 1.
FIG. 5 shows, in a cross-sectional view, a conventional MOS transistor in the high voltage region.
Referring to FIG. 5, the spacer 17 is formed on the sidewall of the gate electrode 9a, and the source/drain 21 is formed in the substrate 1. The source/drain 21 has the low doping part 14 and the high doping part 19.
As discussed hereinbefore, to fabricate MOS transistors in both the high and low voltage regions requires additional processes such as partial removal of the first gate oxide layer 5 in the high voltage region (A). Furthermore, undesirable breakdown may occur in a place 25 between the gate electrode 9a and the drain 21 due to high electric field applied thereto.